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Consumer Electronics
SAT Mixer-Oscillator-PLL TUA6110XS
Data Sheet
16.6.99
V02
Edition 16.02.98 Published by Infineon AG iGr, Marketing-Kommunikation, Balanstr. 73, 81541 Munich (c) Infineon AG iGr 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Office, Semiconductor Group. Infineon AG iGr is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Infineon AG iGr, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Infineon AG iGr. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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TUA6110XS Revision History: Current Version: 16.6.99 Previous Version: 30.7.98 old Page all new Page all Subjects (major changes since last revision) SIEMENS Logo change to Infineon Logo
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
Data Sheet
TUA6110XS
Table of Contents 1 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.3.1 9.3.2 10 11 12 12.1 12.1.1 12.1.2 12.2 12.2.1 12.2.2 12.2.3 13 13.1 13.2 14 15 15.1 15.2
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mixer-Oscillator block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC / DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Digital Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Analog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mixer-Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Band A Circuit Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Band B Circuit Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Measurement of Crystal Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Equivalent I / O-Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application Circuit 1, Band A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Application Circuit 2, Band B (Evaluation Board) . . . . . . . . . . . . . . . . . . . . . . . . . 22
Wireless Group
1
16.6.99
Data Sheet
TUA 6110XS
1
Features
2
Pinning
Mixer/Oscillator * Two 4 pin oscillator for Band A and Band B frequency range * Optimum decoupling of input frequency from oscillator * Double balanced mixer with wide dynamic range and low-impedance input for Band A and Band B frequency range * Internal low-noise reference voltage source PLL * PLL with short lock-in time; no asynchronous divider stage * Fast I2C bus mode possible * 3 programmable chip addresses * Short pull-in time for quick channel access and optimized loop stability * 3 high-current switch outputs * 2 TTL inputs * 5-level A/D converter * Lock-in flag * Power-down flag * Few external components * Full ESD protection
TSSOP 28
3
Ordering Information
Type TUA 6110XS TUA 6110XS Package P-TSSOP-28-1 P-TSSOP-28-1 Tape & Reel Ordering Code Q67001-A5211 Q67007-A5211l
Wireless Group
1
16.6.99
Data Sheet
TUA6110XS
4
Functional Description
The TUA 6110X device combines a mixer-oscillator block including two balanced mixers and two oscillators, with a digitally programmable phase locked loop (PLL) for use in SAT tuners. The mixer-ocillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for Band A/Band B and a low-noise reference voltage source. The PLL block with three hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the sattuner oscillator up to 3.3 GHz in increments of 125 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C bus.
5
Application
The IC is suitable for all SAT-tuners in TV- and VCR-sets, cable set-top receivers and TOPSET-converters for analog TV an Digital Video Broadcasting.
Wireless Group
2
16.6.99
Data Sheet
TUA6110XS
6
Pin Configuration
P-TSSOP 28-1 MIXA 1 MIXAx 2 MIXB 3 MIXBx 4 VVCCA 5 CAS 6 IFout 7 IFoutx 8 GNDD 9 SDA 10 SCL 11 VVCCD 12 Q 13 QX 14 28 OA-B2 27 OA-E2 26 OA-E1 25 OA-B1 24 OB-B2 23 OB-E2 22 OB-E1 21 OB-B1 20 GNDA 19 TUNE 18 CHGPMP 17 P0 / I0 16 P1 / I1 15 P2 / ADC
P-TSSOP-28-1
Wireless Group
3
16.6.99
Data Sheet
TUA6110XS
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Description
Symbol MIXA MIXAx MIXB MIXBx VVCCA CAS IFout IFoutx GNDD SDA SCL VVCCD Q Qx P2/ADC P1/I1 P0/I0 CHGPMP TUNE GNDA OB-B1 OB-E1 OB-E2 OB-B2 OA-B1 OA-E1 OA-E2 OA-B2 Function Band A Mixer input, low-impedance, symmetrical to MIXAx Band A Mixer input, low-impedance, symmetrical to MIXA Band B Mixer input, low-impedance, symmetrical to MIXBx Band B Mixer input, low-impedance, symmetrical to MIXB Positive supply voltage for analog block Chip address select Open collector mixer output, high-impedance, symmetrical to IFoutx Inverse open collector mixer output, high-impedance, symmetrical to IFout Digital Ground Data input/output for the I2C bus Clock input for the I2C bus Positive supply voltage for digital block (PLL) 4 MHz low-impedance crystal oscillator input Inverse 4 MHz low-impedance crystal oscillator input Port output / ADC input Port output / TTL input Port output / TTL input Charge pump output / loop filter VCO tuning voltage output Analog Ground Band B Oscillator amplifier, high-impedance base input, symmetrical to OB-B2 Band B Oscillator amplifier, low-impedance emitter output, symmetrical to OB-E2 Band B Oscillator amplifier, low-impedance emitter output, symmetrical to OB-E1 Band B Oscillator amplifier, high-impedance base input, symmetrical to OB-B1 Band A Oscillator amplifier, high-impedance base input, symmetrical to OA-B2 Band A Oscillator amplifier, low-impedance emitter output, symmetrical to OA-E2 Band A Oscillator amplifier, low-impedance emitter output, symmetrical to OA-E1 Band A Oscillator amplifier, high-impedance base input, symmetrical to OA-B1
Pin No.
Wireless Group
4
16.6.99
Data Sheet
TUA6110XS
8
Block Diagram
CHGPMP GNDA P2/ADC 16 15 fref 13 Qx Q 14 OA-B2 OA-E2 OA-E1 OA-B1 OB-B2 OB-E2 OB-E1 OB-B1 TUNE P1/ I1 17 12 VVCCD
28
27
26
25
24
23
22
21
20
19
18
Oscillator A
Oscillator B
PhaseDet.& ChgPmp
VCO VCOx
Cy
Isolation Amplifier
Isolation Amplifier
Progr. Divider
P0/IO
I/O-PORTS
Ref.Divider
Mixer A
Mixer B
A/B
I2C-Bus Interface
Crystal Oscillator
1 MIXAx MIXA
2 MIXB
3 MIXBx
4 VVCCA
5 CAS
6 IFout
7 IFoutx
8 GNDD
9 SDA
10 SCL
11
Wireless Group
5
16.6.99
Data Sheet
TUA6110XS
9
Circuit Description
9.1 Mixer-Oscillator block
The mixer-oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for Band A/Band and a reference voltage source. In a complete tuner the input signal passes a frontend stage with MESFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input. The input signal is mixed there with the on chip oscillator signal.
9.2 PLL block
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 125 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) divided by Q = 32. The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. If the VCO is not working the PLL locks to a tuning voltage of 33V. By means of control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports P0, P1, P2 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 32) and Cy (divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fQ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 125 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock.
Wireless Group
6
16.6.99
Data Sheet
TUA6110XS
9.3 I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table 1 "bit allocation" should be referred to the following description. All telegrams are transmitted byteby-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Three different chip addresses can be set by appropriate connection of pin CAS (see table 2 "address selection"). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and if VVCCD falls below 3.2 V. It will be reset at the end of a READ operation.
Wireless Group
7
16.6.99
Data Sheet
TUA6110XS
9.3.1
Bit Allocation Read / Write Table1:
Byte MSB1) 1 0 n7 1 A/B 1 POR bit6 1 n14 n6 5I x 1 FL bit5 0 n13 n5 T1 x 0 x bit4 0 n12 n4 T0 x 0 I1 bit3 0 n11 n3 1 x 0 I0 bit2 MA1 n10 n2 1 P2 MA1 A2 bit1 MA0 n9 n1 1 P1 MA0 A1 LSB 0 n8 n0 OS P0 1 A0 Ack A A A A A A A Remarks
Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte 1 Control Byte 2 Read Data Address Byte Status Byte
1. ) MSB shifted first.
Divider ratio: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0
Control Bytes: Bandswitch A/B: A/B=1 OSC/MIX Band B is active Ports P0, P1, P2: P0...P2=1open-collector output is active P0...P2=0open-collector output is inactive, TTL-inputs I1, I0 and ADC available Pump current 5I: 5I=1 high PD output current 5I=0 low PD output current Disabling tuning voltage OS: OS=1 disables TUNE OS=0 enables TUNE
Status Byte: Power On Reset flag POR: flag is set at power-on and reset at the end of READ operation PLL lock flag FL: flag is set to 1 when loop is locked TTL-inputs I1, I0: input data from pins P1/I1, P0/I0 ADC bits A2,A1,A0: digital outputs of the 5-level ADC
Wireless Group
8
16.6.99
Data Sheet
TUA6110XS
Table 2: Address Selection
Voltage at CAS (0...0.1) * VVCC (0.4...0.6) * VVCC (0.9...1) * VVCC MA1 0 1 1 MA0 0 0 1
Table 3: Test Modes
Test mode Normal operation P1 = Cy output, P0 = fref output Charge pump output, CHGPMP is in high-impedance state TTL-inputs I1/I0 are Cy/fref inputs of phase detector T1 0 1 0 1 T0 0 0 1 1
Table 4: A/D Converter Levels
Voltage at P2 / ADC (0...0.15) * VVCC (0.15...0.3) * VVCC (0.3...0.45) * VVCC (0.45...0.6) * VVCC (0.6...1) * VVCC A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0
Wireless Group
9
16.6.99
Wireless Group Addressing Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte
MA1 MA0 R/W
9.3.2 I2C Bus Timing Diagram
Note: SDA 10 Telegram examples:
SCL
Data Sheet
Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop
Start= start condition Addr= address byte DR1= prog. divider byte 1 DR2= prog. divider byte 2 CW1= control byte 1 CW2= control byte 2 Stop= stop condition
TUA6110XS
16.6.99
Data Sheet
TUA6110XS
10 Absolute Maximum Ratings
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Ambient Temperature under bias: TA=-20 to +80 C Limit Values min max
Parameter PLL Supply voltage CHGPMP
Symbol
Unit
Test Conditions
VVCCD VCHGPMP ICHGPMP VQ IQ VSDA ISDA(L) VSCL VP VCAS VTUNE ISDAL IP(L) IP(L) TJ TStg RthSA
-0.3 -0.3
+6
V V mA V mA V mA V V V V mA mA mA C C K/W open collector open collector tmax = 0,1 sec. at 6 V
1 VVCCD -5 -0.3 +6 5 +6 +13 VVCCD +35 5 15 20 +125 -40 +125 130
Crystal oscillator pins Q, Qx Bus input/output SDA Bus output current SDA Bus input SCL Port outputs P0, P1, P2 Chip address switch CAS VCO tuning output (loop filter) Bus output SDA Port outputs P0, P1, P2 Total port output current Junction temperature Storage temperature Thermal resistance (junction to ambient)
-0.3 -0.3 -0.3 -0.3 -1 -1
Wireless Group
11
16.6.99
Data Sheet
TUA6110XS
Parameter Mixer-Oscillator Supply voltage Mix A/B inputs VCO A/B base voltage VCO A/B emitter current IF output
Symbol
Limit Values min max
Unit
Test Conditions
VVCCA VMIXA/B IMIXA/B VOA/B-B IOA/B-E VIFout VIFoutx
-0.3 -5 -0.3 -5
+6 2 6 3 5 6
V V mA V mA V
All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin.
Parameter ESD-Protection1
Symbol
Limit Values min -1 -500 -500 -500 -500 -500 max 1 500 500 500 500 500
Unit
Test Conditions
all pins unless otherwise specified VESD Mixer inputs MIXA/B Mixer outputs IFout / IFoutx Ports Charge pump Oscillator inputs OA/OB VESD MIX VESD IF VESD P VESD CP VESD OSC
kV V V V V Pin 1-4 Pin 7, 8 Pin 15-17 Pin 18 Pin 21-28
1. according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
Wireless Group
12
16.6.99
Data Sheet
TUA6110XS
11 Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Limit Values min +4.5 +4.5 +4.5 256 420 900 900 1400 -20 max +5.5 +5.5 +5.5 32767 920 1400 2150 2650 +80 MHz MHz MHz MHz C V V V open collector
Parameter Supply voltage Supply voltage Mixer output voltage Programmable divider factor Mixer A input frequency range Oscillator A frequency range Mixer B input frequency range Oscillator B frequency range Ambient temperature
Symbol VVCCD VVCCA VIFout VIFoutx N fMIXA fOA fMIXB fOB Tamb
Unit
Test Conditions
Wireless Group
13
16.6.99
Data Sheet
TUA6110XS
12 AC / DC Characteristics
Supply Voltage Ambient temperature VVCCA = 5 V, VVCCD = 5 V Tamb = 25 C Limit Values min typ max
Parameter
Symbol
Unit
Test conditions
12.1 Digital Unit 12.1.1 PLL
Supply current Crystal frequency Crystal resistance Oscillation frequency Input impedance Charge pump output CHGPMP HIGH output current LOW output current Tristate current Output voltage HIGH output current LOW output voltage 12.1.2 I2C-Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current Bus output SDA (open collector) HIGH output current LOW output voltage Edge speed SCL,SDA Rise time Fall time Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time tsusta thsta 0.6 0.6 s s fSCL tH tL 0 0.6 1.3 400 kHz s s tr tf 300 300 ns ns IOH VOL 10 0.4 A V VOH = 5.5 V IOL = 3 mA VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A VIH = VS VIL = 0 V ICPH ICPL ICPZ VCP ITH VTL 1.0 90 22 220 50 +1 2.5 10 0.5 300 75 A A nA V A V 5I = 1, VCP = 2 V 5I = 0, VCP = 2 V T0 = 1, VCP = 2 V locked VTH = 33 V, T0 = 1 ITL = 1.0 mA IVCCD fQ RQ fQ ZQ 21 3.2 10 3,99975 -600 4,000 -750 26 4.0 31 4.8 100 -900 mA MHz VVCCD = 5 V series resonance series resonance fQ = 4 MHz fQ = 4 MHz Crystal oscillator connections Q, Qx
4,00025 MHz
Drive output TUNE (open collector)
Wireless Group
14
16.6.99
Data Sheet
TUA6110XS
Parameter Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA Pulse width of spikes which are suppressed Capacitive load for each bus line HIGH output current LOW output voltage TTL port inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current ADC port input P2 HIGH input current LOW input current Address selection input CAS HIGH input current LOW input current
Symbol
Limit Values min 0.6 1.3 0.1 0 200 0 50 400 1 0.5 2.7 0.8 10 -10 10 -10 50 -50 typ max
Unit
Test conditions
tsusto tbuf tsudat thdat Vhys tsp CL IPOH VPOL VPIH VPIL IPIH IPIL IADCH IADCL ICASH ICASL
s s s s mV ns pF A V V V A A A A A A VCASH = 5 V VCASL = 0 V VPIH = 13.5 V VPIL = 0 V VPOH = 5 V IPOL = 15 mA
Port outputs P0, P1, P2 (open collector)
Wireless Group
15
16.6.99
Data Sheet
TUA6110XS
Parameter
Symbol
Limit Values min typ max
Unit
Test conditions
12.2 Analog Unit 12.2.1 Mixer-Oscillator
Current consumption Mixer current IVCCA IVCCA IIF RIFout Mixer output impedance CIFout 0.5 pF 14 14 4 20 20 6 11 26 26 8 mA mA mA k Parallel equivalent circuit, fIF = 479,5 MHz Parallel equivalent circuit, fIF = 479,5 MHz fMIXA = 950 MHz fMIXA = 950 MHz Vd = 0,5..28 V VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on fm = 10 kHz, application circuit 1 fMIXA= 420 MHz (DSB), fIF=479.5MHz fMIXA= 920 MHz (DSB), fIF=479.5MHz fMIXA = 420 MHz (DSB), fIF=479.5MHz fMIXA = 920 MHz (DSB), fIF=479.5MHz VMixA = 80 dBV Bit A/B=0 Bit A/B=1
12.2.2 Band A Circuit Section
Mixer input impedance Oscillator frequency range RMIXA LMIXA fOscA fOscA Oscillator drift fOscA fOscA Oscillator phase noise L(fm) GMixA Mixer gain GMixA FMixA Mixer noise figure FMixA IF suppression aIFB 8 10 20 13 dB dB 3 8 6 10 8 13 dB dB 3 -78 6 8 900 20 10 1400 2 2 5 nH MHz MHz MHz MHz dBc/Hz dB
Wireless Group
16
16.6.99
Data Sheet
TUA6110XS
Parameter
Symbol
Limit Values min typ 20 10 1400 2650 2 2 5 -65 3 6 2 8 10 15 20 8 3 13 18 max
Unit
Test conditions
12.2.3 Band B Circuit Section
Mixer input impedance Oscillator frequency range RMIXB LMIXB fOscB fOscB Oscillator drift fOscB fOscB Oscillator phase noise L(fm) GMixB Mixer gain GMixB FMixB Mixer noise figure FMixB IF suppression aIFB dB dB dB dB nH MHz MHz MHz MHz dBc/Hz dB fMIXB = 950 MHz fMIXB = 950 MHz Vd = 0,5..28 V VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on fm = 10 kHz, application circuit 2 fMIXB = 950 MHz (DSB), fIF=479.5MHz fMIXB = 2150 MHz (DSB), fIF=479.5MHz fMIXB = 950 MHz (DSB), fIF=479.5MHz fMIXB = 2150 MHz (DSB), fIF=479.5MHz VMixB = 80 dBV
Wireless Group
17
16.6.99
Data Sheet
TUA6110XS
13 Test Circuit
13.1 DC and RF Parameter Measurement
4.7n
4.7n
+33V 4.7n
22k BB545 BB545 BB833
22k BB833 22k 33k
22k
22k
22k
22k
1.8n
27k
8.2n 5.6p 5.6p 22p 22p
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA 6110XS
1 2 3 4 5 6 7 8 9 10 11 12 13
4MHz
14
47p 2 4 balun 1 5
47p 2
47p 4 balun 1 5
47p 10n 6.8p 6.8p
100p
100p
18p
220
220
4.7n
100n
VVCCA CAS
balun: TOKO B4F 617DB-1023
IF output
SDA SCL VVCCD
Wireless Group
18
16.6.99
Data Sheet
TUA6110XS
13.2 Measurement of Crystal Oscillator Frequency
VVCC IVCC Q 18 pF 4 MHz
5V 5k P0
Test mode: T1 = HIGH T0 = LOW
fref Counter 5k
fQ = fref * 32
TUA 6110XS
P1 fcy Counter
fVCO = fcy * N N: divider ratio
GNDD
Wireless Group
19
16.6.99
Data Sheet
TUA6110XS
14 Equivalent I / O-Schematic
15
16
17
18
19
20
21
22
23
24
25
26
27
Wireless Group
28
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16.6.99
Data Sheet
TUA6110XS
15 Application Circuits
15.1 Application Circuit 1, Band A
1n +33V 1n
22k BB545 BB545 1k 8.2
33k +5V
22k
22k 2.2n printed 22k 2.7k 2.7k 2.7k
5.6p
5.6p
22n
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA 6110XS
1
2.2p 22p 22p 4.7n 4.7n 33 33 220 220 4.7n
2
3
4
5
6
7
8
3.3p
9
10
11
12
13
4MHz
14
100p
100p
18p
4.7n 100k
132n 1n 1n
4.7n
VVCCA CAS
SDA SCL
VVCCD
IF output
Wireless Group
21
16.6.99
Data Sheet
TUA6110XS
15.2 Application Circuit 2, Band B (Evaluation Board)
4.7n
+33V 4.7n
100 BB835 BB835 1k 33k +5V 8.2
Stripline l=7.0mm w=0.75mm Stripline l=7.0mm w=0.75mm
22k
1.8n
27k
2.7k
2.7k
2.7k
printed 22p 22p
8.2n
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TUA 6110XS
1 2 3 4 5 6 7 8 9 10 11 12 13
4MHz
14
47p 2 4 balun 1 5
47p
4.7n
4.7n 10u
100p 6.8p 220
100p
18p
220 4.7n
4.7n
6.8p
100k
4.7n
VVCCA CAS
balun: TOKO B4F 617DB-1023 Note: PCB material: FR4, h=1.25mm
IF output
SDA SCL VVCCD
Wireless Group
22
16.6.99

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